This invention relates generally to an improved high-voltage timing circuit for a MOS dynamic memory element.
There have been attempts to improve the characteristics of high-density dynamics memory elements such as action margin by using word line drive signals with voltage level higher than the source voltage. In conventional circuits, however, the delay time becomes too long if an attempt is made to obtain such a high voltage, and this has been one of the difficulties which prevented the elements from acquiring improved speeds.
FIG. 7 shows a conventional circuit which has been in general use for dynamic memory elements and its timing diagram is shown in FIG. 8. In FIG. 7, Nos. 1 and 2 each represent an ordinary timing circuit. The output voltage from each stage is equal to the source voltage V.sub.CC. Nos. 31 and 32 are circuits for generating active low delay signals, each determining the delay time between input and output signals for the circuit. The conventional method to construct a timing circuit with a high-voltage output by using such conventional circuits was to link the ordinary timing circuits 1 and 2 in series as shown in FIG. 7 and to make use of a MOS capacitor 4.
When this circuit generates a high-voltage output signal, the precharge signal .phi..sub.P becomes high during a precharge period as shown in FIG. 8 while the output .phi..sub.OUT and node B.sub.2 are precharged to the ground potential level and nodes A.sub.1 and A.sub.2 to high levels. The input .phi..sub.IN remains at the ground level during this precharge period. When the precharge signal .phi..sub.P drops to the ground level and the input signal .phi..sub.IN is inputted during the sebsequent active period, the MOS capacitor of the first-stage timing circuit begins to be charged and when its charging has been sufficiently completed, the delay circuit output A.sub.1 drops and the boost node 6 is boosted beyond V.sub.CC, causing the output signal .phi..sub.OUT to start rising through a MOS field-effect transistor (hereinafter called MOST) 7. Let the time of delay in this period be denoted by td1. The MOS capacitor 4 for boosting the output signal begins to charge as the output signal .phi..sub.OUT rises. Let td2 be the time it takes to charge it approximately to the level of V.sub.CC`. Since the MOS capacitor 4 generally has a large capacitance, the aforementioned charging time td 2 has a large value. When the charging of the MOS capacitor 4 has been completed, node A.sub.2 begins to drop; the node 8 in the second-stage timing circuit reaches a high level; the MOST 9 becomes conductive; the node 6 in the first-stage timing circuit is discharged to the grund level; the MOST 7 is cut off; the node 11 is boosted higher than V.sub.CC by the MOS capacitor 10; B.sub.2 rises through the MOST 12; and the output signal .phi..sub.OUT connected through the MOS capacitor 4 is boosted higher than the source voltage. Let td3 be the delay time of this period.
In summary, it requires a time period of td1+td2+td3 from the input of signal .phi..sub.IN until the desired high output voltage .phi..sub.OUT is obtained. In general, however, this required time is unnecessarily long, having a detrimental effect on the access time.
In other words, since two stages of a timing circuit are connected in series according to the conventional method, the time of delay becomes more than twice as long as if a single-stage timing circuit is used. Moreover, the boost capacitor 4 with large capacitance must be charged to a substantial degree during the active period and the time required for this charging has a limiting effect on the operating speed of the timing circuit.